The invention relates to a circuit for producing a polarity-reversed voltage with opposite polarity to a power supply voltage.
Generally, when the withstand voltage of a transistor is raised, the impurity concentration of its semiconductor substrate is set up to be lower. If the concentration is so set up, however, the threshold voltage V.sub.th of the transistor, for example, a MOS-FET (metal oxide semiconductor field effect transistor) inevitably becomes lower. For this reason, a back-gate bias must be applied to the substrate in order to obtain an MOS-FET with high withstand voltage and high threshold voltage V.sub.th. It has been known that, when a back gate voltage is applied between the source of the MOS-FET and the substrate, the back-gate bias effect raises the threshold voltage V.sub.th of the MOS-FET corresponding to the voltage value applied. In this case, the polarity of the back-gate bias to be applied to the substrate electrode must be opposite to that of the power supply voltage for the MOS-FET. In other words, a polarity-reversed voltage with opposite polarity to the power supply voltage must be produced for the back-gate biasing. Further, it is desirable that the polarity-reversed voltage is effectively produced and its value is always constant.
One form of the conventional circuit for producing a polarity-reversed voltage with opposite polarity to the power source voltage (hereinafter referred to a polarity-reversed voltage) is illustrated in FIG. 1. In the figure, a couple of n-channel MOS-FETs connected in series are connected between a power supply voltage +V.sub.DD and a ground potential point E. A clock signal .phi. is applied to the gate of the transistor 1 and a clock signal .phi. is applied to the gate of the transistor 2. The clock signal .phi. is an antiphase signal of the clock signal .phi., as a matter of course. Assume that a first level of each clock pulse .phi. and .phi. are +V.sub.DD and -V.sub.DD (H level) and a second level thereof is 0 level (L level). The connection point of the first and second transistors is coupled with the input terminal of a capacitor 3. Between the output terminal of the capacitor 3 and the ground potential point E is connected an n-MOS FET 4 of which the gate is connected to the output terminal of the capacitor 3. A diode 6 is inevitably formed between the source or drain of a transistor 4 and the substrate when the polarity-reversed voltage producing circuit shown in FIG. 1 is integrated. The output terminal 5 of the polarity-reversed voltage, i.e. the voltage with opposite polarity to that of the +V.sub.DD, is coupled with the output terminal of the capacitor 3, through the diode 6 connected with the polarity as shown. The substrate electrodes of transistors 1, 2 and 4 are connected to the polarity-reversed voltage output terminal 5. If necessary, a second capacitor 7 is connected between the terminal 5 and the ground potential point E.
In the circuit in FIG. 1, when the clock signal .phi. is at H level (+V.sub.DD or active level), the clock signal .phi. is at L level (ground level or non-active level) so that the transistor 1 is rendered conductive and the transistor 2 is rendered nonconductive. Accordingly, the voltage level V.sub.1 at the input terminal of the capacitor 3 becomes H level, i.e. +V.sub.DD level. When the level at the input terminal of the capacitor 3 becomes +V.sub.DD level the voltage level V.sub.2 at the output terminal of the capacitor 3 also goes positive as the voltage level V.sub.1 at the input terminal of the capacitor 3 goes positive. Here, the threshold voltage of the n-channel transistor 4 is expressed by V.sub.th. When the voltage level at the output terminal of the capacitor 3 exceeds the threshold voltage V.sub.th, the transistor 4 is rendered conductive and the voltage level V.sub.2 at the output terminal of the capacitor 3 is kept at the ground potential so that the potential difference across the capacitor 3 is kept at approximately +V.sub.DD.
At this time, the clock signal .phi. becomes L level and the clock signal .phi. becomes H level with the result that the transistor 1 is rendered nonconductive while the transistor 2 is rendered conductive. Accordingly, the voltage level V.sub.1 at the input terminal of the capacitor 3 approaches from +V.sub.DD level to the ground level. As described above, the voltage level V.sub.2 at the output terminal of the capacitor 3 is sustained at approximately ground level, and therefore the voltage level V.sub.2 at the output terminal of the capcitor 3 becomes lower than the ground level, that is to say, it becomes negative voltage level. Since the negative voltage or potential is applied to the gate of the transistor 4, the transistor 4 is rendered nonconductive. The negative voltage appearing at the output terminal of the capacitor 3 is taken out from the terminal 5 through the diode 6. The second capacitor 7 is used to keep the output voltage at the terminal 5 constant value. As described above, the circuit shown in FIG. 1 enables a voltage with opposite polarity to the +V.sub.DD to be derived from the output terminal 5.
The convention circuit shown in FIG. 1, however, has the following disadvantages. Since the desired polarity-reversed voltage is taken out from the terminal 5 through the diode 6, the polarity-reversed voltage value is reduced by an amount of the forward voltage drop of the diode 6. Another disadvantage is that, since the back-gate bias is applied to a number of FETs (not limited to the one shown) through the terminal 5, the back-gate bias current also flows through the diode 6. Accordingly, when the back-gate bias current changes, the forward voltage drop of the diode 6 also changes and therefore the value of the polarity-reversed voltage is not constant.
Accordingly, an object of the invention is to provide a circuit for producing a polarity-reversed voltage with opposite polarity to a power supply voltage in which the loss of the polarity-reversed voltage is minimum and the voltage level thereof is invariable.